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Development of ANALOG-DIGITAL Converter IP SARADC and OS-SARADC
Development of low-power, small-area ADC IP SARADC and OS-SARADC
We are developing low-power, small-area SARADC IP for low-power sensors.
SARADC IP has 12-bit resolution and a conversion speed of 10Msps, and the power consumption including the VREF buffer is kept very low. It Area is also very compact.
OS-SARADC IP achieves 16-bit resolution by oversampling SARADC. The resolution is increased by reducing the conversion speed to 100Ksps. Like SARADC IP, it consumes very low power and has a compact area.
Compared to our conventional SARADC IP, it has significantly reduced power and area.
SARADC IP has 12-bit resolution and a conversion speed of 10Msps, and the power consumption including the VREF buffer is kept very low. It Area is also very compact.
OS-SARADC IP achieves 16-bit resolution by oversampling SARADC. The resolution is increased by reducing the conversion speed to 100Ksps. Like SARADC IP, it consumes very low power and has a compact area.
Compared to our conventional SARADC IP, it has significantly reduced power and area.
Characteristics table of our ADCs
Based on many years of research and development and abundant experience, we develop highly original ADCs and provide them to our customers.
| PLADC | CYADC | SARADC | OS-SARADC | DSADC | |
|---|---|---|---|---|---|
| Development year | 2021 | 2021 | 2023 | 2023 | 2024 |
| Process (nm) | TSMC 180 | TSMC 180 | TSMC 180 | TSMC 180 | TSMC 180 |
| Power supply voltage (V) | 3.3 | 3.3 | 1.8 | 1.8 | 1.8 |
| Resolution (bit) | 16 | 16 | 12 | 16 | 24 |
| Conversion speed (sps) | 50M | 8.5M | 10M | 100K | 48K |
| SNR (dBFS) | 80 | 81 | 69 | 79.5 | 100 |
| VREF buffer Built-in or not | Built-in | Built-in | Built-in | Built-in | Built-in |
| Status | Evaluated | Evaluated | Evaluated | Evaluated | Under Development |
The development details of PLADC(pipeline ADCs) and CYADC(cyclic ADCs) are provided below.
Features of SARADC IP/OS-SARADC IP
High power efficiency
- Low power consumption design including VREF buffer
- High power efficiency due to unique circuit design
Built-in VREF buffer
- No need for external VREF circuit
Clockless
- Only one timing signal input (When operating at 10Msps, input 10MHz as timing signal)
Dynamic operation
- Reduce power consumption by lowering conversion speed.
Figure 1. Conversion speed and power efficiency
Small Area
- Compact layout design
Input switching function
- Can switch multiple inputs and input them to the ADC.
ADC IP Availability and Process Porting
We are providing the SARADC IP and OS-SARADC IP. In addition, we also provide porting services to processes according to customer requests. If you are interested, please feel free to contact us. We also provide buffer IP for input capacitance drive that supports both SARADC IP and OS-SARADC IP.
Evaluation results of SARADC IP/OS-SARADC IP
Thorough evaluation that supports high quality
We are evaluating the performance of SARADC IP/OS-SARADC IP using our own evaluation board.
The evaluation results are currently being prepared.
The evaluation results are currently being prepared.
We not only design semiconductor circuits, but also perform IC prototyping, evaluation environment development, and evaluation consistently.
We can propose and provide an environment for evaluating the characteristics of IP using our own evaluation board and evaluation system. We also accept requests to build a dedicated evaluation environment according to specifications and requests, so please contact us.
We can propose and provide an environment for evaluating the characteristics of IP using our own evaluation board and evaluation system. We also accept requests to build a dedicated evaluation environment according to specifications and requests, so please contact us.