Development of circuit boards and systems for ADC evaluation

High-performance ADC evaluation system enables fast and accurate evaluation of IC characteristics.
At SANEI HYTECHS, we pursue highly accurate evaluation technology that minimizes the influence of the external environment to enable accurate measurement of high-performance analog circuits. In particular, we have developed a system that enables high-speed data collection and analysis for ADCs, and also provide dedicated evaluation systems that are compatible with custom ASICs.
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High-speed data collection and analysis system for high-performance ADC

Performance evaluation of high-performance ADCs is becoming more difficult as technology advances. In particular, the higher the resolution, the longer the evaluation time tends to be.
Therefore, we have developed an evaluation environment that allows ICs equipped with high-speed, high-resolution ADCs to be evaluated accurately in a short time.

Features

We provide a system that can efficiently perform the measurements and analysis required for ADC evaluation with the following configuration.

Operation measurement at socket possible

Supports high-speed operation of 16-bit, 50Msps.

DC characteristic measurement

Precise measurement of INL, DNL, ​​etc. is possible.

AC characteristic measurement

Characteristic evaluation of SNR, SNDR, SFDR, etc.

Simple configuration

Operates with one DC power supply and PC. (signal is generated by IC on board)

High-speed measurement

Smooth data collection with FPGA and PC software

Temperature characteristic acquisition

Temperature-dependent characteristic evaluation is possible using Thermostreamer

Dedicated evaluation system compatible with custom ASICs

We also provide a dedicated evaluation environment for custom ASICs tailored to IC specifications. By using an existing ADC evaluation system as a base, rapid development is possible.
The evaluation software is written in Python.
The evaluation environment process will be explained using the operation image of INL/DNL measurement (Ramp mode) as an example.

Operation procedure of the evaluation software

  1. Start the Python software from the command line of the PC.
  2. Start USB communication with the evaluation board and perform initial settings.
  3. Repeat the following operations a specified number of times. (3 times in the figure)
    1. Write 1 to the measurement start register of the FPGA.
    2. The FPGA generates ramp data and sends DAC input data.
    3. Counts up the code up to 65,536.
    4. The DAC outputs a ramp wave and inputs it to the ADC of the TEG through the AMP.
    5. The FPGA receives the ADC output code.
    6. The FPGA stores the results in the DRAM on the evaluation board in order.
    7. When 6,5536 data sets are collected, the measurement is complete and the PC reads the data together via USB.
  4. Performs statistical processing such as tallying and averaging the measurement data.
  5. Outputs the results to a CSV file.
  6. Reads the CSV file in Excel and calculates INL/DNL.
Research and Development