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Algorithm Design
We can meet a wide range of needs, from zero-based network design to development support and consulting.
SANEI HYTECHS offers various algorithm design services tailored to our clients' needs, drawing on the insights gained through our unique artificial intelligence (AI) research. We can be flexible in responding to our clients' requests, including full-scratch design, development support, and lightweight network optimization for edge devices.Algorithm Design Service
Full scratch design of an algorithm
We design neural network architectures and other algorithms from scratch, tailored to their specific applications
Algorithm refinement
Improving the accuracy and/or reducing the weight of algorithms based on the customer's initial ideas
Co-development approach
Working closely with the customer from research on papers to algorithm design and device implementation
Design achievements
We have a track record of serving a diverse range of clients from various industries, including major automotive companies, large electronics manufacturers, image-related companies, and others.
Main business achievements
Segmentation algorithm development, Provision and support of learning environments (consulting)
Segmentation algorithm development, Provision and support of learning environments (consulting)
Semantic segmentation
We have streamlined PixelNet to enable implementation of semantic segmentation algorithms on FPGA and MPU platforms.
We have reduced the input image size and the number of input/output channels in each processing layer, such as decreasing the number of input/output channels in the convolutional layer from 512ch to 32ch.
We were able to reduce the number of parameters by 90% using these techniques.
After retraining and evaluation, we confirmed that the accuracy (mIoU) was not significantly different from before the reduction.
Moreover, we optimized the lightweight PixelNet for hardware implementation on FPGA and MPU platforms.
We employed techniques such as fixed-point quantization of parameters to 16 bits and division of the processing of convolutional layers in the latter stage to be performed immediately after bilinear interpolation.
Please refer to "Edge Device Implementation: Demo: High-Speed Execution of Semantic Segmentation on FPGA (Zynq UltraScale+)" for the results of the implementation.
We have reduced the input image size and the number of input/output channels in each processing layer, such as decreasing the number of input/output channels in the convolutional layer from 512ch to 32ch.
We were able to reduce the number of parameters by 90% using these techniques.
After retraining and evaluation, we confirmed that the accuracy (mIoU) was not significantly different from before the reduction.
Moreover, we optimized the lightweight PixelNet for hardware implementation on FPGA and MPU platforms.
We employed techniques such as fixed-point quantization of parameters to 16 bits and division of the processing of convolutional layers in the latter stage to be performed immediately after bilinear interpolation.
Please refer to "Edge Device Implementation: Demo: High-Speed Execution of Semantic Segmentation on FPGA (Zynq UltraScale+)" for the results of the implementation.
Other examples of algorithms that can be designed.
At SANEI HYTECHS, we conduct research on algorithms for image and speech analysis for a wide range of applications and devices.
For more information, please visit our Research and Development page.
For more information, please visit our Research and Development page.
Adding depth data to RGB images
Multimodal system design