Delta Sigma (ΔΣ) ADC IP development

Development of 24-bit ΔΣ ADC IP that achieves high resolution, low power consumption, and compact size.
SANEI HYTECHS is developing ΔΣ ADC (DSADC) IP that achieves low power consumption and compact size for high-precision sensors. DSADC IP features 24-bit high resolution and a conversion speed of 48Ksps (3.072MHz sampling, 64 oversampling). This ADC targets low-frequency band signals from DC to the voice band. As an ADC circuit with a VREF buffer, we aims for low power consumption and compact size.
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Characteristics table of DSADC

The characteristics of the DSADC IP developed by we are as follows.
* Delta Sigma ADCs are currently under development. Values are target values.
Development year 2024
Process（nm） TSMC 180
Power supply voltage（V） 1.8
Resolution（bit） 24
Conversion speed（sps） 48K
SNR（dBFS） 100
VREF buffer Built-in or not Built-in
Status Under Development

Other in-house developed ADC IP characteristics

We have developed highly original ADC technology and provide it to our customers, taking advantage of our many years of research and development and extensive experience.Detailed characteristics of other in-house developed ADC IPs can be viewed at the link below.

Characteristics table of in-house developed ADC IP

Features of DSADC IP

Ideal for high-precision conversion in low frequency bands

Compared to pipeline ADCs and SARADCs, this ADC is suitable for converting low frequency band signals with high precision.

High linearity and excellent noise characteristics

Excellent linearity and noise characteristics enable high-precision conversion.

Flexible characteristic adjustment

By changing the characteristics of the digital filter, you can flexibly adjust the conversion speed, bandwidth, resolution, etc.

High precision with low oversampling

64 times oversampling is used as standard, enabling high-precision conversion even with low oversampling.

Discrete type configuration

The discrete ΔΣADC configuration makes the input a capacitive load.
Development and Developing ADC product
Development and Developing ADC product

Block diagram of DSADC IP

3rd order 4bit Delta Sigma
3rd order 4bit Delta Sigma

Development status of DSADC IP

We are currently proceeding with the circuit design to meet the "Characteristics table of our ADC IP". We plan to prototype the DSADC IP in the near future. If you are interested in the development status and detailed specifications of the DSADC IP, please feel free to contact us.
Research and Development