SARADC / OS-SARADC IP development

Development of low-power, small-area ADC IP SARADC and OS-SARADC
We are developing low-power, small-area SARADC IP for low-power sensors.
SARADC IP has 12-bit resolution and a conversion speed of 10Msps, and the power consumption including the VREF buffer is kept very low. It Area is also very compact.
OS-SARADC IP achieves 16-bit resolution by oversampling SARADC. The resolution is increased by reducing the conversion speed to 100Ksps. Like SARADC IP, it consumes very low power and has a compact area.
Compared to our conventional SARADC IP, it has significantly reduced power and area.
INDEX

Characteristics table of SARADC and OS-SARADC

The characteristics of the SARADC and OS-SARADC IP developed by we are as follows.
  SARADC OS-SARADC
Development year 2023 2023
Process (nm) TSMC 180 TSMC 180
Power supply voltage (V) 1.8 1.8
Resolution (bit) 12 16
Conversion speed (sps) 10M 100K
SNR (dBFS) 69 79.5
VREF buffer Built-in or not Built-in Built-in
Status Evaluated Evaluated

Other in-house developed ADC IP characteristics

We have developed highly original ADC technology and provide it to our customers, taking advantage of our many years of research and development and extensive experience.Detailed characteristics of other in-house developed ADC IPs can be viewed at the link below.

Characteristics table of in-house developed ADC IP

Features of SARADC IP/OS-SARADC IP

High power efficiency

  • Low power consumption design including VREF buffer
  • High power efficiency due to unique circuit design

Built-in VREF buffer

  • No need for external VREF circuit

Clockless

  • Only one timing signal input (When operating at 10Msps, input 10MHz as timing signal)

Dynamic operation

  • Reduce power consumption by lowering conversion speed.
Figure 1. Conversion speed and power efficiency

Small Area

  • Compact layout design

Input switching function

  • Can switch multiple inputs and input them to the ADC.

Evaluation results of SARADC IP/OS-SARADC IP

Thorough evaluation that supports high quality
We are evaluating the performance of SARADC IP/OS-SARADC IP using our own evaluation board.
The evaluation results are currently being prepared.

Provision of in-house developed ADC IP and process porting

Our SARADC and OS-SARADC IP can be provided for various applications. We also provide custom design services based on the process and specifications according to your needs. If you are looking for an ADC IP solution, please feel free to contact us. We also provide buffer IP for input capacitance drive that supports both SARADC IP and OS-SARADC IP.

In-house Developed Analog IP Service

We provide high-performance analog IP that meets our customers' needs in a short delivery time.

Provision and support of evaluation environment

We not only design semiconductor circuits, but also integrate IC prototyping, development of evaluation environments, and evaluation. The following issues are particularly important for analog circuits.
  • The effects of semiconductor element mismatch
  • Changes in power supply and temperature
  • The effects of power supply and circuit board noise
  • The effects of parasitic resistance and parasitic capacitance
Due to factors such as those mentioned above, it is said to be difficult to achieve device performance as designed. We pursue advanced evaluation technology to eliminate these external factors as much as possible and accurately measure high-precision circuit characteristics. For more information on evaluation boards and systems, please see the link below.

Development of circuit boards and systems for ADC evaluation

High-speed, high-precision ADC evaluation system makes IC characteristic evaluation more efficient. We also can support custom ASIC.
Research and Development